Systolic arrays are a pipe network arrangement of processing elements that allow data to flow synchronously between neighboring processing elements. Each processing element may receive data from one or more neighboring PE, process the data, and transmit the processed data to one or more neighboring processing element. In a two dimensional systolic array, data may be passed horizontally and vertically between PEs every clock cycle. Systolic arrays have been used in applications such as signal processing, linear algebra, string matching, sorting/searching, and other applications.
The dedicated communication paths between processing elements and the processing elements' ability to be configured to support pipelining allow systolic arrays to be efficient when performing computations. For example, for some operations, a systolic array may be able perform computations in O(n) time instead of O(n3) time as required by other processing structures.
Target devices, such as field programmable gate arrays (FPGA), are good candidates for systolic array implementation due to their parallel reconfigurable hardware. FPGAs are constructed with tiling blocks of memory and logic which match well with the requirements of systolic arrays. The programmable input outputs of FPGAs also work well with the high input output requirements of systolic arrays.
Designers responsible for programming FPGAs to implement systolic arrays are required to have extensive knowledge in both the algorithm performed by the systolic array and hardware acceleration. Designers are also met with the challenge of tuning the performance of the system which may be difficult and time consuming using hardware description language.